Project Overview

In the Signals and Systems I (EE 224) course in Iowa State's Electrical Engineering curriculum, the students have been using the CyDAQ device to enhance their lab experience and deliver real-world results. Currently, the device allows students to measure and record electrical signals that are being input to the device, and outputs those measurements into graph files. Due to the hardware on the device not being properly utilized by inefficient firmware, the data transfer time is very high and requires a lot of waiting to be sent to the user's computer. There are also bugs within the user interface that have been causing issues for the students completing and TA's administering the labs; such as data not displaying correctly on the CyDAQ graphs or the user interface not being user-friendly.

Our proposed solution to these problems is to rework the firmware from the ground-up, utilizing the dual-core functionality of the CyDAQ for faster processing power and increasing the efficiency of the firmware code. The CyDAQ will also be implemented with USB communication to the host computer rather than UART, increasing the sampling speed to 10 MSps (internal) and 1 to 2 MSps (external). The User Interface will be completely redone in another language, using PyQt and focusing on intuitive and adaptable design. The design of the User Interface will primarily focus on making it easy for TAs or other senior design groups to add future functionality. This will be done by creating thorough documentation and following common coding conventions.

Final Documents

Weekly Reports

Design Documents